Backside Illumination

Most of today’s CMOS imagers are illuminated from the front side and a compromise must be made between the area allocated for necessary electrical wiring and the size of the photodiode. This leads to a reduction in light sensitivity characterized by the ratio of photosensitive area to the total area exposed to light. In imagers this ratio is approximately the size of the photosensitive element divided by the size of the pixel called fill factor. To overcome the sensitivity reduction due to a fill factor < 100%, micro lenses have been introduced to the CMOS process. Driven by consumer demands, competitive, imagers must offer multi megapixel resolution at low cost which can only be achieved by a reduction in pixel dimension. But as pixels continue to shrink, it becomes more and more difficult to guide enough light to the photosensitive element through the frontside metallization of a CMOS IC. At pixel dimensions below 1.45 micron, CMOS image sensor manufacturers introduced backside illumination.

Backside illuminated CCDs are known to provide superior sensitivity and are therefore the preferred sensor choice in cameras for machine vision, scientific or other high end application. However, the desired imager performance for these applications can in many cases not be achieved if the device is designed using a conventional BSI CMOS process that has been optimized for cell phone cameras. This has several reasons:

  • 1. The employed silicon has low resistivity and good pixel registration is only possible if the charge collection region is kept small relative to the pixel pitch.
  • 2. Today’s BSI CMOS sensors are based on pinned photodiodes which create image lag, especially if the pixel is larger than the target value for the process.
  • 3. The silicon membrane is very thin to minimize the spreading of charge in the field free region outside the photodiode. This eliminates NIR sensitivity at wavelength of ~640nm and beyond which is often desired for non-consumer applications.

SCI developed a CMOS BSI process specifically to overcome these limitations. We use high resistivity silicon for our imagers and a vertical drift field can be created in the thick silicon membrane by applying a voltage to the backside contact . Thereby the benefits of fully depleted backside illuminated CCD and CMOS imagers are combined in one monolithic device with up to now unachievable performance.

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Fig: Above figure represents BSI Technology developed at SCI